1. Field of the Invention
This invention relates to a logarithmic intermediate-frequency amplifier, and more particularly, to a logarithmic intermediate-frequency amplifier having true logarithmic characteristic or pseudo logarithmic characteristic.
2. Description of the Related Art
In general, a logarithmic intermediate-frequency (IF) amplifier comprises IF amplifiers cascade-connected to each other in a multistage connection manner, rectifiers for receiving output signals of these IF amplifiers in a successive manner, and an adder for adding all output signals of these rectifiers to each other, and is generally formed on a bipolar integrated circuit. This is based on such advantageous facts that bipolar transistors have superior noise characteristics as well as low sensitivity degradation when considered from the viewpoint of a received input, and it can be driven even at a low impedance or at a large capacity because the bipolar transistor has a high drivability and the like.
Recently, a C-MOS logarithmic IF amplifier has been demanded to be developed in order to effectively use the advantages of the C-MOS integrated circuit. In this case, however, the following problems have been pointed out on a structural basis;
An MOS transistor is large in l/f noise, so that it is required to have an intermediate-frequency (IF) band cut off its low band side in order to prevent the sensitivity from being degraded from the viewpoint of a received input. So-called HPF (High Pass Filter) characteristic to cut off this low band side can be equivalently obtained by providing IF amplifiers to a multistage cascade-connection manner through coupling capacitors. In this case, however, a coupling capacitor to be inserted is desired to be small in capacity, On the other hand, the multistage connection of the IF amplifiers through the coupling capacitors makes that the rectifiers receiving output signals of respective IF amplifiers differentiate the signal waveforms thereof, thus making it easy to vary the direct-current value of an output of each rectifier. As a result, in order to obtain a good linear logarithmic characteristic, it is unavoidably required to expand the frequency band of an input signal of each rectifier to the low frequency side, that is, it is required that the capacity of a coupling capacitor to be inserted is increased.
Accordingly, in order to practically realize the C-MOS logarithmic IF amplifier, such a problem has arisen is that for the capacity of a coupling capacitor to be used, such contradictory requirements as shown above must be satisfied. In addition, in case that the capacity of a coupling capacitor to be used is increased, there arises a problem on the drivability of the IF amplifier itself as well.
Next, as a pseudo--logarithmic IF amplifier of a polygonal line approximation type formed on a C-MOS integrated circuit, such a circuit as is, for example, shown in FIG. 1 is known conventionally. This circuit is disclosed in the Japanese Laid-Open patent application No. 62-292010, which comprises n differential amplifiers respectively including MOS transistor pairs (T01, T01), (T02, T02), . . . and (TOn, TOn) and constant-current sources I01, I02, . . . and I0n. These differential amplifiers are cascaded in a n-stage connection manner. The differential amplifiers of the first through nth stages are connected to full-wave rectifiers comprising two pairs of transistors (T11 and T1k), (T21 and T2k), . . . and (Tnl and Tnk), and n constantcurrent sources I11, I12, . . . and I ln for driving these two pairs of transistors, respectively. The differential amplifier of the (u+1)th stage has a full-wave rectifier comprising two pairs of MOS transistors (T(n+1), and T(n+1)k) and two constant-current sources In(n+1) for driving the two pairs of them, and receiving an output signal of the differential amplifier at the nth stage.
These 2(n+1) pairs of transistors (T11 and T1k), (T21 and T2k), . . . and (T(n+1)l and T(n+1)k) forming full-wave rectifiers each has a gate-width (W) and gate-length (L) ratio (W/L) of 1:k (k&gt;1) thereby to constitute an unbalanced differential pair. Then, in respective two pairs, the transistors having a gate-width (W) and gate-length (L) ratio (W/L) of one (1), or (T11 and T11), (T21 and T21), . . . , and (T(n+1)1 and T(n+1)1) have the drains and gates connected respectively in common, and on the other hand, those having the ratio (W/L) of k, or the transistors (T1k and T1k), (T2k and T2k), . . . and (T(n+1)k and T(n+1)k) have the drains and gates connected respectively in common.
Next to the (n+1) th stage, an adder comprising three MOS transistor pairs (T10, T20), (T80, T40) and (T50, T60) is provided, which sums up the outputs of the full-wave rectifiers of the first to the (n+1)th stages.
With the pseudo-logarithmic IF amplifier arranged as above, the operation will be described below.
First, a transconductance parameter .alpha. can be expressed in terms of the gate-width and gate-length ratio (W11/L11) of the transistor T11 on the first stage by the following equation (1); EQU .alpha.=.mu.n(Cox/2) (W1/L1) (1)
where, .mu.n is a mobility of MOS transistor; and Cox is a gate oxide film capacity per unit area.
In addition, with the transistor pair (T11, T1k) on the first stage, a ratio k between the gate-width and gate-length ratio of one transistor T11 of the pair and that of the other transistor T1k can be expressed as follows: ##EQU1##
Further in addition, in the two pairs of transistors (T11 and T1k) of the first stage, if the gate-to-source voltages of respective transistors are expressed as Vgs1, Vgs2, Vgs3 and Vgs4, and the threshold voltage of each transistor is expressed as Vt, the currents of respective transistors I1, I2, I3 and I4 can be expressed as follows; EQU I1=(Vgs1-Vt).sup.2 ( 3) EQU I2=k.alpha.(Vgs2-Vt).sup.2 ( 4) EQU I3=.alpha.(Vgs3-Vt).sup.2 ( 5) EQU I4=k.alpha.(Vgs4-Vt).sup.2 ( 6)
Here, these currents I1, I2, I3 and I4 can be expressed in terms of a current I11 of the constant-current source of the first stage as follows: EQU I1+I2=I11 (7) EQU I3+I4=I11 (8)
Also, an input voltage VIN of the two pairs of transistors (T1l and T1k) of the first stage can .be expressed in terms of the gate-to-source voltages Vgs1, Vgs2, Vgs3 and Vgs4 of the transistors as follows; EQU VIN=Vgs1-Vgs2=Vgs4-Vgs3 (9)
As a result, an output current .DELTA.I1 of the two pairs of transistors (T1l and T1k) can be expressed as follows: ##EQU2##
From Eq. (10), it can be found that the output current .DELTA.I1 has a square full-wave rectification characteristic with respect to the input voltage VlN.
In the same manner as above, an output current .DELTA.I2 of the two pairs of transistors (T2l and T2k) of the second stage. . . , and an output current In+1 of the two pairs of the transistors (T(n+1)1 and T(n+1)k) can be respectively expressed as follows: ##EQU3##
Here, it is clear that the output currents .DELTA.I1, .DELTA.I2. . . , .DELTA.In+1 and the constant-current sources I11, I22, . . . , and In(n30 1) of respective stages are related as shown by the following equations (13) to (15); EQU -2I11.ltoreq..DELTA.I1.ltoreq.2I11 (13) EQU -2I22.ltoreq..DELTA.I2.ltoreq.2I22 (14) EQU -2In(n+1).ltoreq.In+1.ltoreq.2In(n+1) (15)
This means that even if the input voltage VIN and the output voltages V1, V2 . . . . , VOUT of respective stages are made large, the output currents .DELTA.I1, .DELTA.I2, . . . .DELTA.In+1 are always within the respective ranges shown by Eqs. (13) to (15). In addition, the .voltage V1, V2 . . . VOUT are output voltages of the differential amplifiers of respective stages, and as the input voltage ][IN is increased gradually, these voltages are successively saturated in the order of VOUT, . . . V2, and V1.
Also, the output current IOUT of the adder consisting of the three MOS transistor pairs (T10, T20), (T30, T40) and (T50, T60) can be expressed as follows: EQU IOUT=.DELTA.I1+.DELTA.I2+. . . +.DELTA.In+1 (16)
As a result, by suitably setting the constant current values I01, I02, . . . and I0n of the constant-current sources of respective stages and the resistance values R01. R02, . . . , and ROn of resisters to be connected to the drains of respective transistors, the maximum output voltages of the differential amplifiers of respective stages can be made of a constant sign. This means that the characteristic of the output current IOUT can be made approximately of a logarithmic characteristic to the input voltage VIN.
With the conventional pseudo-logarithmic IF amplifier arranged as shown above, it makes one full-wave rectifier of two unbalanced differential transistor pairs and as a result, the number of constant-current sources required is twice the number of rectifiers, resulting in a problem of large current consumption. In addition, considered from the viewpoint of the circuit structure, one rectifier uses two unbalanced differential transistor pairs and as a result, the circuit scale disadvantageously becomes large.
This invention was made with a view to solving the above-mentioned problems, an object of this invention is to provide a logarithmic IF amplifier in which contradictory requirements on the capacity of a coupling capacitor to be inserted can be satisfied thereby to be formed on a C-MOS integrated circuit.
Another object of this invention is to provide a pseudo-logarithmic IF amplifier capable of reducing power consumption as well as decreasing circuit scale.
As the applications related to this invention, the followings are concerned; the Japanese Patent Application No. 2-292866 previously made by the same applicant; the U.S. patent application No. 784,502 which was made correspondingly thereto; and the British, German and French Patent Application No. 91310038.4 based on the European Patent Convention.